1. Field of the Invention
The invention relates to a method for fabricating a SONOS memory.
2. Description of the Prior Art
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased electrically.
Product development efforts in memory device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Some of the flash memory arrays today utilize a gate structure made of dual polysilicon layers (also refers to as the dual poly-Si gate). The polysilicon layer utilized in these gate structures often includes a dielectric material composed of an oxide-nitride-oxide (ONO) structure. When the device is operating, electrons are injected from the substrate into the bottom layer of the dual polysilicon layers for storing data. Since these dual gate arrays typically store only one single bit of data, they are inefficient for increasing the capacity of the memory. As a result, a flash memory made of silicon-oxide-nitride-oxide-silicon (SONOS) is derived. Preferably, a transistor from these memories is capable of storing two bits of data simultaneously, which not only reduces the size of the device but also increases the capacity of the memory significantly. The operation of a typical SONOS memory is described below.
During the programming of a typical SONOS memory, electrical charge is transferred from a substrate to the charge storage layer in the device, such as the nitride layer in the SONOS memory. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to become trapped in the charge storage dielectric material. This jump is known as hot carrier injection, in which the hot carriers being the electrons. Charges are trapped near the drain region as the electric fields are strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the charge storage dielectric layer near the source region. Since part of the charge storage dielectric layer are electrically conductive, the charge introduced into these parts of the charge storage dielectric material tend to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous charge storage dielectric layer.
Please refer to FIGS. 1-6. FIGS. 1-6 illustrate a method for fabricating a SONOS memory according to the prior art. As shown in FIG. 1, a semiconductor substrate 12 is provided, in which the semiconductor substrate 12 is preferably composed of gallium arsenide (GaAs), silicon on insulator layer, epitaxial layer, silicon germanium, or other common semiconductor substrate materials. Next, a silicon oxide layer 14, a silicon nitride layer 16, a silicon oxide layer 18, and a polysilicon layer 20 is formed on the semiconductor substrate 12.
Next, as shown in FIG. 2, a pattern transfer process is conducted by utilizing a patterned photoresist (not shown) as a mask to perform an etching process for removing a portion of the polysilicon layer 20, the silicon oxide layer 18, the silicon nitride layer 16, and the silicon oxide layer 14. The result produces a stacked gate 22 on the semiconductor substrate 12. The stacked gate 22 is preferably composed of a control gate formed by a portion of the polysilicon layer 20 and an ONO structure formed by a portion of the silicon oxide layer 14, the silicon nitride layer 16, and the silicon oxide layer 18. Accordingly, the silicon nitride layer 16 can be used as a charge storage layer while the memory cell is being programmed or erased.
As shown in FIG. 3, an ion implantation process (not shown) is performed by using the stacked gate 22 as a mask to form a source/drain region 24 in the semiconductor substrate 12 beside the two sides the stacked gate 22.
As shown in FIG. 4, an inter-layer dielectric 28 is formed on the semiconductor substrate 12 and the stacked gate 22. Another pattern transfer process is conducted by using a patterned photoresist (not shown) as a mask to perform an etching process for forming a plurality of contact holes (not shown) in the inter-layer dielectric 28. Thereafter, a metal composed of tungsten is deposited on the inter-layer dielectric 28 and into each of the contact holes. A plurality of contact plugs 30 is then formed in the inter-layer dielectric 28.
As shown in FIG. 5, a metal interconnection process is conducted by first forming a plurality of inter-metal dielectrics 32 and 34 on the inter-layer dielectric 28 and a plurality of metal interconnects 36 connected to the contact plugs 30.
As shown in FIG. 6, a passivation layer 38 is deposited on the surface of the top metal interconnects 36. A pattern transfer process is conducted by forming a patterned photoresist (not shown) as a mask to perform an etching process for forming an opening in the passivation layer 38. After the opening exposes the top patterned metal interconnect, a contact pad 40 is formed.
After the formation of the contact pad 40, an annealing process is performed to reduce the chance of electrical malfunctioning and facilitate a much more even voltage distribution. Subsequently, an ultraviolet treatment is performed to release the charges accumulated during the fabrication process of the memory cell. In most cases, charges accumulated within the memory device during the fabrication process would often induce in uncontrollable threshold voltage and often result in damage of the entire device.
Please refer to FIG. 7. FIG. 7 illustrates the threshold voltage of a SONOS memory during different stages of the fabrication process according to the prior art. As shown in FIG. 7, when the annealing process is performed, the distributing range of the threshold voltage is approximately 1.5V. It should be noted that in the conventional method for fabricating a SONOS memory, the annealing process is conducted after the formation of the contact pad 40 and before the ultraviolet treatment. This order of fabrication releases charges stored in the charge storage layer but also increases the distributing range of the initial threshold voltage, which ultimately narrows the sensing boundary during the programming or erasing stage of the SONOS memory and increases the chance of miscalculations.
Additionally, the annealing process performed would reduce the voltage of the high voltage cells and cause the voltage of the cells to approximate to the main distribution region. However, the ultraviolet treatment performed after the annealing process, which often has the ability to increase the voltage of voltage cells, would not only increase the voltage of the low voltage cells but also raise the voltage of the high voltage cells to a much higher state. The end result would cause the central value of the overall electrical distribution to be higher than the neutral state.